An electrically programmable read only memory (EPROM) is a type of device which has a plurality of floating gates that are either charged or not charged. Some EPROMs are programmed by channel hot-electron injection which is initiated by grounding the source, biasing the drain to a voltage usually higher than the supply voltage, and taking the control gate to a voltage sufficiently high to cause charge accumulation within the floating gate. Typically, the control gate programming voltage is between about 10 volts to 20 volts. Many EPROMs use ultraviolet radiation to remove electrons from the floating gate. However, there are other EPROMs in which the whole memory array is erased at one time and are referred to as flash EPROMs. One type of flash EPROM has a tunnel dielectric which is usually a thin oxide between the floating gate and the substrate as described in U.S. Pat. No. 4,780,424 issued to Holler (hereinafter referred to as Holler). Such a device is erased by disconnecting the drain, grounding the control gate, and taking the source to a sufficiently positive voltage, typically between 10 V and 20 V, to remove the accumulated charge from the floating gate through the tunneling process. The parameters and method used for programming and erasing vary greatly between devices, but devices which are erased by taking the source to a high electrical potential may have problems if the source-channel junction breakdown voltage is too low. As will be described later, these problems with the device arise during erasing if the channel of the device has been doped.
The device has field isolation regions between the circuits within the memory array. The source and drains may lie below the field oxide, or they may be directly adjacent to the field oxide. These circuits have a channel which is the area immediately beneath where the tunnel dielectric is subsequently formed and between the source diffusion junction and the drain diffusion junction. Before the floating gates are formed over those channels, the channels are doped. In the prior art, channel doping has been performed as a blanket doping across the memory array. By a blanket doping, it is meant that there is no mask covering any portion of the memory array. The dopant enters the entire surface of the memory array. The dopant is usually introduced into the substrate by ion implant. During ion implant, the ions do not travel through the thick field oxide. The same ions travel through a thinner dielectric which resides in the interfield oxide regions (regions between the field oxide regions), part of which becomes the channel. A good example of this process is described in Holler in which the amount of dopant within the channel is relatively uniform across the lateral area of the channel. Therefore, the doping concentration within the channel near the source is about the same as the doping concentration near the drain.
Many EPROMs have more than one channel dopant. A particular prior art process has two key channel doping steps. The first doping step, referred to as enhancement implant (ENI), adjusts the threshold voltage of the device. A key design consideration requires that the dopant remain relatively close to the silicon-tunnel dielectric interface. A second channel doping step referred to as punchthrough adjust implant (PCHI) increases the voltage required to cause current to flow between the source and the drain while the gate is at ground potential. PCHI goes deeper into the substrate than the ENI. Both of these implants affect the erasing of the EPROM device described above.
During the erasing of a flash EPROM as previously described, the source voltage is taken to a high potential. A high source voltage during erasing is required to initiate the electron tunneling process through the tunnel dielectric which lies between the floating gate and the channel. Unfortunately, this high source voltage can be near or above the source-channel junction breakdown voltage depending on the channel doping concentration at the source end. The amount of substrate current is primarily governed by the source-channel junction breakdown. Once the source-channel junction has been broken down, the electrons flow much more freely between the substrate and the source causing a large substrate current. If the source voltage during erasing is less than the source-channel junction breakdown voltage, the electrons in the substrate have a much harder time flowing to the source. As will be discussed later, high substrate current is to be avoided, and therefore, the source-channel junction breakdown voltage must be higher than the source voltage during erasing.
Consequently, the voltage on the source during erasing may be limited by the breakdown voltage of the source-channel junction. A relatively lower source-channel junction breakdown voltage leads to a number of problems during erase. First, a lower source-channel junction breakdown voltage means that substrate current during erasing is higher. During erasing, the substrate current can reach 10 .mu.A per cell and may exceed 20 .mu.A per memory cell when the source voltage is very low. High substrate current is both a reliability and design problem. It is a reliability problem in that high substrate current may generate more holes which are injected into tunnel dielectric and cause problems discussed below. Higher substrate current means the device runs hotter and may cause layers within the device to crack or sever. As a design issue, the substrate current generates more noise which could propagate to other circuits within the device and interfere with the operation of the device.
Lower source voltage increases the number of holes that are injected into the tunnel dielectric during erasing. The holes within the dielectric degrade the capacitive properties of the tunnel dielectric, so that the dielectric is not able to support as much electrical field. In addition, holes within the tunnel dielectric could cause charge loss from a programmed floating gate. Eventually, enough charge loss creates a state such that the voltage on the floating gate is at an indeterminate value which is between a fully programmed state and an erased state. The transistor could become "leaky", meaning that the floating gate electrons disappear and therefore, a programmed cell could become an erased cell. Such a state is not desired in an EPROM. Hole injection into the tunnel dielectric during erasing must be kept low. A number of prior art attempts are described immediately below. All of the prior art attempts discussed below focus on raising the source-channel junction breakdown voltage.
Semiconductor junction breakdown is governed by classical diffused junction breakdown mechanics described in many semiconductor physics textbooks. Decreasing the source doping concentration in a given device increases the source-channel junction breakdown voltage. Reducing the doping concentration of the source has not been a desired solution because the source must be highly conductive. In a contactless electrically programmable and electrically erasable memory device of the flash EPROM type, the source contacts have been purposely kept to the outer areas of the array so that multiple contacts within the array do not need to be made. As such, the source must be very conductive along the entire length of the array. If the source dopant would be reduced, the conductivity of the source would also be reduced resulting in higher source resistances than as determined by the device design. The higher source resistance slows down the access time of the device.
Another prior art attempt has been to grade the source doping concentration even more. With the memory cell of Holler, the source was formed by two separate ion implants. The first implant uses arsenic implant which keeps the arsenic dopant relatively closer to the silicon-field oxide interface and the second implant uses phosphorus which diffuses faster than arsenic. The faster diffusing phosphorous is at the source-channel junction. If the source junction were to be graded even further, more phosphorous or some other n-type dopant would be further into the channel. As the source-channel junction gets closer to the drain-channel junction, the punchthrough voltage is reduced which is not desired. Therefore, further grading of the source junction is not possible.
Another prior art attempt to increase the source-channel junction breakdown voltage could include reducing or eliminating the ENI concentration for the entire channel. The device requires the ENI dose to be kept sufficiently high enough so that the programming characteristics of the EPROM remain the same. More specifically, the dopant at the drain segment of the channel needs to remain unchanged since the device as described herein uses channel hot-electron injection from the drain side to program the memory cell. The programming characteristics of the memory cell remain the same since the doping concentration for the drain segment is unchanged. The reduced or eliminated ENI could adversely affect the read threshold voltage of the device. No ENI would produce a very leaky transistor to the point where current could flow between the source and drain such that a programmed cell within the same column of the memory array could be read as an unprogrammed cell. A reduced or no ENI would not be a solution.
The last prior art attempt to increase the source-channel junction breakdown voltage could include reducing or eliminating the PCHI concentration within the entire channel. The function of PCHI is to increase the voltage required to cause current to flow between the source and drain (punchthrough voltage). As the PCHI concentration decreases, the punchthrough voltage becomes lower. A desired characteristic of the device has a relatively high punchthrough voltage which allows closer spacing between the source and the drain. This increases the number of die per substrate and increases yield as the same device occupies less area which reduces the chances that the device has a fatal silicon crystal defect. Therefore, lowering the PCHI concentration would not be a solution to the current problem.